Getting Started with SuperFlash® Technology
Microchip offers a wide range of NOR Flash products in a variety of bus interfaces, speeds, voltages and packages. Below are some things to consider when selecting a Flash solution:
| NAND | NOR | |
|---|---|---|
| Main Application | File Storage | Code execution |
| Storage capacity | High | Low |
| XIP Capabilities | No | Yes |
| Cost per bit | Better | |
| Active Power | Better | |
| Standby Power | Better | |
| Write Speed | Good | |
| Read Speed | Good |
NOR Flash is available with either a serial or parallel bus interface. The choice of which bus to use is often dictated by the required data rates of the application as well as the amount of available I/O on the microcontroller and the board space available. With the ongoing demand for smaller and cheaper products, more designs are now being switched to a serial interface to reduce board space and component price.
| Parallel | Serial SPI | |
|---|---|---|
| Data Throughput | High | Medium |
| Pin Count | 32+ | 8+ |
| Package Size | Large | Small |
| Power Consumption | Medium | Low |
| Cost | High | Low |
Today’s microcontrollers are often bond pad-limited. This means that the size of the die is limited by the space needed for bond pads rather than for the microcontroller gates / circuitry. Eliminating bond pads results in a smaller die, increasing the amount of die on a wafer and resulting in reduced cost per die. Additionally, more pins increase the assembly and packaging costs of both the microcontroller and the memory. This is why there has been a major shift from using parallel Flash to using serial Flash. However, switching to fewer pins means lower data throughput. In order to offset this, a quad I/O serial interface is being used in the latest serial devices to create SQI™ Flash devices.
Common Flash Memory Interface (CFI) is an open standard approved by JEDEC. The goal of the standard is to allow interchangeability between Flash memory devices from different manufacturers of parallel Flash products. Each manufacturer’s memory has differences in performance specifications, memory maps and features. The standard allows for this identifying information to be read out of a table of values stored on the Flash device. The benefit of using this standard is that information about multiple Flash parts no longer needs to be stored in system software. This helps to future-proof the software and allows developers to use lower-cost Flash devices as they become available without needing to update their software.
Execution In Place (XIP) refers to executing program code directly from external storage rather than copying it into RAM first. Running program code from external storage allows additional RAM to be freed up for dynamic data. For XIP to be possible, you must have random access capability, the appropriate memory mapping and sufficient bandwidth. NOR Flash is well suited for execution in place whereas NAND Flash is not. Program code in NAND Flash must be copied into RAM before being executed.
The Serial Flash Discoverable Parameter (SFDP) standard is similar to the CFI standard for parallel Flash. The goal of this JEDEC approved standard is to allow interchangeability between Flash memory devices from different manufacturers. Each manufacturer’s memory has differences in performance specifications, memory maps and features. The standard allows the use of a single driver which reads identifying information out of a table of values stored on the Flash device. The benefit of using this standard is that information about multiple Flash parts no longer needs to be stored in system software. This helps to future-proof the software and allows developers to use lower-cost Flash devices as they become available without needing to update their software.